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Chip Design Magazine
July/aug Contents
- Smaller, Faster and More Parasitic
- SystemVerilog and VMM Overcome WiMAX Verification Challenges
SystemVerilog and VMM-based environment help achieve first pass silicon success by performing smarter verification quicker. - SystemVerilog Comes of Age
The Open Verification - DSP-Core Evolution Powers Advancements in Communications and Multimedia Technologies
Market-specific DSPs will form the basis of nextgeneration SoCs - High-Level Synthesis Improves Productivity without Sacrificing Area, Performance, or Power
The cost of design is starting to come down with top quality and faster results. - The Impact of 3D Packaging
A quick guide to when, why, and how to stack your next design. - The Impact of 3D Packaging
A quick guide to when, why, and how to stack your next design. - Editor's Note−Reader Wants Print, not Links
- In the News-People in the News
- Behind the Numbers-FPGA Vendors Throw Kitchen Sink at Power-Consumption Issues
- Max’s Chips & Dips−The Way Things Were
- Top View−Take a System-Level View of IP Integration
- Dot.Org--Accellera Technical Sub-Committee Enables VIP Interoperability and Reuse
- No Respins-- Women in Technology: Crashing the Silicon Ceiling
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Volume: July/August 2009
Smaller, Faster and More Parasitic
Consumers’ love for ever-smaller electronic products translates to increased circuit performance and higher transistor density at lower and lower technology nodes, such as 45nm, 28nm and beyond. But these nodes are fraught with design and manufacturing challenges that weren’t really a problem at the relatively spacious geometries of 130nm and above.Also in this Issue
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